A High Speed Motion Estimator Using 2-D Log Search Algorithm

This paper describes the design of a high speed motion estimator using the Z-D log search algorithm. The architecture consists of 5 simple processing elements (PE) where each PE is capable of computing the sum-of-absolute-difference (SAD) to exploit the parallelism. For each step in the 2-D log search procedure, the 5 SADs of the 5 search points are computed in parallel. The design is implemented using Verilog and synthesized using Synopsys. Simulations show that the architecture is able to generate the motion vector for each 16*16 macroblock in 14.58~s for 3-step log search, and 24.30~s for 5step log search. The architecture is thus well suited for encoding MPEG2 video up to MP@ML. The architecture is divided into two independent units: a SAD unit and a Motion Vector Generation unit (MVG). The current frame is input into the SAD in real-time. The reference frame stored in memory is also fed to the SAD. For an MPEG application macroblocks (MB) of 16* 16 pixels are used as units for motion estimation. The SAD unit computes the SADs between the current macroblock and the reference macroblock. The MVG unit generates the minimum SAD for each step in the 2-D log search procedure. This result is fed back to the SAD unit so that the PEs within it can appropriately change its search points. Eventually, the MVG unit outputs the coordinates of the motion vector, MOTION-X and MOTION-Y, of the macroblock in question. In the SAD unit, based on the search points, five corresponding pixels, pixrefl, pixret2, pixref3, pixref4, pixref5, from five locations in the reference frame memory are fed to the five PEs. Each PE computes the absolute difference between the current MB’s pixel and the reference MB’s pixel pointed to by a search point. The process repeats until all 256 pixels in a MB are compared and five SADs are obtained and stored in five SAD registers. The outputs of the PE’s, SAD registers, SADI, SAD5 SAD3, SAD4, SAD& are fed to the MVG unit to determine which one is the minimum. The MVG unit uses one 16-bit comparator to determine which of SAD& SAD2, SAD3, SAD4, SADS, is the minimum.The result is fed back to the SAD unit for another round of computation. Execution continues until the minimum SAD is in SADl, the SAD register of the center PE. At this time, the distance between search points can be reduced if needed (say to f 1 or to k 0.5 pixels) and the process repeats. Finally, the X and Y registers of SAD1 hold the motion vector and is output from the chip.